The present invention relates to an integrated circuit design, and more particularly, to an embedded memory with a setup-hold time that can be controlled internally or externally and an associated integrated circuit.
In general, a system-on-chip (SoC) uses lots of embedded memories. In the SoC design phase, the traditional timing sign-off may reserve a 3-sigma local variation factor for hold-time margin. However, a defective parts per million (DPPM) level covered by 3-sigma is obviously smaller than 1000 DPPM. If the reserved hold-time margin is increased from 3-sigma to 6-7 sigma, the DPPM can be improved. However, the DPPM is improved at the expense of chip area, timing closure and speed performance. As a result, the SoC design suffers from chip area, timing closure and speed performance, inevitably. Further, in a silicon debug phase, the memory built-in self-test (MBIST) logic of the embedded memory is unable to identify hold-time violations at the memory input interface and the MBIST logic itself. This may result in holes in the MBIST Shmoo plot.